1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to an organic thin film transistor (OTFT) made by plasma treating organic semiconductor interface surfaces.
2. Description of the Related Art
As noted in Wikipedia, an organic field-effect transistor (OFET) is a transistor that uses an organic semiconductor in its channel. OTFTs are a type of OFET. OTFTs can be prepared either by vacuum evaporation of small molecules, by solution-casting of polymers or small molecules, or by mechanical transfer of a peeled single-crystalline organic layer onto a substrate. These devices have been developed to realize low-cost, large-area electronic products. OTFTs have been fabricated with various device geometries.
FIG. 1 is a partial cross-sectional view of a bottom gate TFT (prior art). The most commonly used device geometry is a bottom gate with top drain and source electrodes, because this geometry is similar to the thin-film silicon transistor (TFT) using thermally grown Si/SiO2 oxide as gate dielectric. In contrast to a metal-insulator-semiconductor FET (MISFET) or metal-semiconductor FET (MESFET), in a top gate TFT the source and drain electrodes are directly deposited onto the conducting channel (a thin layer of semiconductor). Then a thin film of insulator is deposited between the semiconductor and the metal gate contact. A bottom gate TFT reverses the structure.
Organic polymers, such as poly(methyl-methacrylate) (PMMA), CYTOP, PVA, polystyrene, parylene, etc., can be used as a dielectric. OFETs employing numerous aromatic and conjugated materials as the active semiconducting layer have been reported, including small molecules such as rubrene, tetracene, pentacene, diindenoperylene, perylenediimides, tetracyanoquinodimethane (TCNQ), and polymers such as polythiophenes (especially poly 3-hexylthiophene (P3HT)), polyfluorene, polydiacetylene, poly 2,5-thienylene vinylene, poly p-phenylene vinylene (PPV). These can be deposited via vacuum or solution base methods, the later being of interest for printed electronics. The newer generation of solution processable organic semiconductors consists of blends of high performance small molecule and polymeric molecules for optimum performance and uniformity.
Various strategies are being devised to improve the device performance of all solution processed, printed organic transistor devices. One of the crucial elements for improving device performance is optimization of the semiconductor and source/drain electrode interfaces in order to obtain good ohmic contacts with very low contact resistance. In the case of organic semiconductor TFTs, the metal source drain electrodes are typically coated with a surface treatment layer (e.g., a thiol layer) in order to tune the energy level alignment and reduce the energy barrier for charge injection. These surface treatments rely on pristine metal surfaces for optimum effectiveness. This condition is easily possible in the case of evaporated metals, and reducing the time between the deposition and the surface treatment steps and has been shown to work well.
In the case of printed organic transistor devices, the metal is typically deposited using some solvent based ink with a number of additives that enable good ink printing properties. Organic printed electronics also use a solution and/or print process to deposit the semiconductor and dielectric TFT layers. Inkjet (IJ) printing is commonly used. Metallic silver nanoparticle (NP) based inks are currently the most popular candidate for printing the gate and source-drain layers of organic devices. In the case of printed metals, however, it is hard to obtain a clean pristine surface for two reasons: (i) the electrodes are typically annealed in air for 15-30 minutes to drive off the solvents and sinter the metal NPs; and, (ii) a residue of solvents and additives from the inks typically results in contamination of the metal surface. This leads to a non-ideal surface treatment and, consequently, results in poor contact properties.
The morphology and patterning of the organic semiconductor (OSC) layer of an OTFT is another challenging problem. Two key areas of research involve optimization of the grain growth in the OTFT channel region, and the isolation of the channel region of the device from the surrounding areas. To successfully IJ print an OSC layer, the solution must be optimized, as well as the surface energy over a large area of the substrate, to accurately control the extent of the OSC drop spread and uniformity. This is essential so that the consequent morphology is as desired and consistent from device to device.
It would be advantageous if the surfaces of printed electrodes and dielectric material could be treated to improve the quality of the interface with a subsequently deposited organic semiconductor.
It would be advantageous if the above-mentioned treatment process could also improve the uniformity and size of organic semiconductor crystal grains, for better device performance.